1. Field of the Invention
The invention relates to leadframes for semiconductor packages and in particular to leadframes for high frequency applications.
2. Description of the Related Art
Semiconductor dies are enclosed in plastic packages that provide protection from hostile environments and enable electrical interconnection between the semiconductor die and a printed circuit board via a metal leadframe. The conventional leadframe type semiconductor package has a central supported die pad for supporting semiconductor die, a plurality of leads peripherally located therein, a plurality of bonding wires for electrically connecting the semiconductor die to the leads, and a mold compound, such as plastic, for encapsulating these components in a package structure.
In most semiconductor package configurations, a portion of the leadframe is internal to the package, (i.e., completely surrounded by the mold compound). Portions of the leads of the leadframe typically extend externally from the package body for electrically connecting the package to the printed circuit board.
In the electronics industry, there is continued demand for developing semiconductor dies which have increasing processing speeds and higher degrees of integration. For a semiconductor package to accommodate these enhanced semiconductor dies, the number of leads included in the semiconductor package must be significantly increased. To avoid an undesirable increase in the size of the semiconductor package attributable to the increased number of leads, a common practice is to reduce or narrow the spacing between the leads. However, a decreased spacing between the leads increases the capacitance between the leads, and increases the level of self inductance and mutual inductance. This inductance adversely affects the quality of signals transmitted on the leads of the leadframe by increasing signal reflections; causing greater impedance mismatches.
Especially, in high frequency applications the semiconductor package has the greatest influence on total performance of the circuit, and one of the main causes of performance degradation is inductance of the interconnections between chip and printed circuit board. Therefore, as the operating frequency of these circuits increases, there is a need for even lower impedance mismatches packages. As shown in FIG. 2A, conventionally, the lead route or lead distribution of the leadframe is substantially symmetrical for desired producibility or manufacturability and lower process cost, but do negatively affect the impedance match.